% activate debug output
verbose y 

experimentName 2.5D-SIC
======design=====================
% no design cost 
D_nreCost 0


====== manufacturing =====================
%total production, assume 1 shipped IC 
M_productionVolume 1

======manufacturing: wafer=====================

%number of dies in stack and their labels
M_dieCount 4
M_dieLabelList 1 2 3 4

M_cost_wafer 700 3000 3000 3000

M_enableArea 0 0 0 0 

M_diesPerWafer 400 1000 1000 1000 
M_yield_die 0.99 0.99 0.99 0.99 

%TSV yields, they are not used in F2F stacked 2.5D-SICs
M_yield_TSV 1.00 1.00 0.95 1.00

% which relation to use between yield, fault coverage and test escapes
% in this case equation 0 must be used (see manual).
M_testEscapeEquation 0

M_stackOp1 3-4 | D2D, F2B
M_stackOp2 1-2 | W2D, F2F
M_stackOp3 1-3 | W2D, F2F

% all stacking operation (three in this example) are assumed to be 10 cent
M_cost_stackOp a 0.10

%the yield of the dies during stacking
M_yield_die_stackOp1  1.00 1.00 0.99 0.99
M_yield_die_stackOp2  0.99 0.99 1.00 1.00
M_yield_die_stackOp3  0.99 1.00 0.99 1.00

%the yield of the interconnects during stacking
M_yield_int_stackOp1  0.99 1.00 1.00
M_yield_int_stackOp2  1.00 0.99 1.00
M_yield_int_stackOp3  1.00 1.00 0.99

======packaging=====================
%packaging 2.00 per 3D-SIC with 100% yield
P_cost 2.00
P_yield_die a 1
P_yield_int a 1


====== test ============================

======== test order  =========
T_testOrder i1 i2 i3 d1 d2 d3 d4 

%all dies and interconnects are tested one by one (serially) in the stack
T_parallelTest_die {1}{2}{3}{4}
T_parallelTest_int {1}{2}{3}

======== test cost die =========
%pre-bond tests for active dies and final test for all dies
%no pre-bond test for bottom die
T_cost_die_prebond  0.00 1.50 1.50 1.50
T_cost_die_stackOp1 0.00 0.00 0.00 0.00
T_cost_die_stackOp2 0.00 0.00 0.00 0.00
T_cost_die_stackOp3 0.00 0.00 0.00 0.00
T_cost_die_packaged 0.10 1.50 1.50 1.50

======== test cost interconnects =========
%TSVs/microbumps are not tested in the pre-bond phase
% interconnects are tested during mid-bond and post-bond
% interconnects are tested during final/packaging test
T_cost_TSV_prebond  0.00 0.00 0.00 0.00
T_cost_int_stackOp1 0.10 0.00 0.00
T_cost_int_stackOp2 0.00 0.10 0.00
T_cost_int_stackOp3 0.00 0.00 0.10
T_cost_int_packaged 0.10 0.10 0.10

======== FC die =========
T_fc_die_prebond  0.00 0.99 0.99 0.99
T_fc_die_stackOp1 0.00 0.00 0.00 0.00
T_fc_die_stackOp2 0.00 0.00 0.00 0.00
T_fc_die_stackOp3 0.00 0.00 0.00 0.00
T_fc_die_packaged 1.00 0.99 0.99 0.99

% no prebond test (die 3 has a TSV yield)
T_fc_TSV_prebond  0.00 0.00 0.00 0.00
T_fc_int_stackOp1 0.00 0.00 0.00
T_fc_int_stackOp2 0.00 0.00 0.00
T_fc_int_stackOp3 0.00 0.00 0.00
T_fc_int_packaged a 1.000000

T_probedDie_stackOp1 1
T_probedDie_stackOp2 1
T_probedDie_stackOp3 1


======logistics=====================
% No logistics cost  

L_dieBased n

L_cost_company2waferfab 0.00
L_cost_waferfab2tester a 0.00
L_cost_tester2fab3D_wafer a 0.00
L_cost_tester2fab3D_stack a 0.00
L_cost_fab3D2tester a 0.00
L_cost_tester2packaging 0.00
L_cost_packaging2tester 0.00
L_cost_tester2company 0.00
L_cost_waferfab2fab3D a 0.00
L_cost_fab3D2packaging 0.00
L_cost_packaging2company 0.00
L_cost_fab3D2fab3D a 0.00

======sweep ======================
% analyze impact of pre-bond fault coverage and its associated test cost (dim 1) versus its defect density (dim 2). 
% This is performed for bottom die only
Sweep 3 2                         
SweepParam1 -dim 1 T_cost_die_prebond[1] -b 0.0  -e 0.2  -s 0.02 
SweepParam2 -dim 1 T_fc_die_prebond[1]   -b 0.0  -e 1.0  -s 0.10
SweepParam3 -dim 2 M_defectDensity[1]    -b 0.0002 -e 0.001 -s 0.0002